1. Technical Field
The present invention disclosed herein relates to a semiconductor device package, and more particularly, to a semiconductor chip stacked package.
2. Description of the Related Art
Packaging technology for integrated circuits has been under continual development to meet requirements for miniaturization and packaging reliability in the semiconductor industry. For example, the requirement for miniaturization has accelerated technological progress related to a package having a size close to that of a semiconductor chip, sometimes referred to as a chip scale package (CSP). Moreover, the packaging reliability requirement raises the importance of a packaging technology that is capable of improving the efficiency of packaging processes and the mechanical and electrical reliability after packaging.
Also, as further miniaturization and higher performance of electronic equipment is required, various technologies are under development to provide high-capacity semiconductor products. One method of providing the high-capacity semiconductor products includes improving the capacity of a memory chip, i.e., providing a high degree of integration in the memory chip. A higher number of cells is directly integrated in the limited space of the semiconductor chip to achieve the high degree of integration.
However, the high degree of integration in the memory chip requires the use of more advanced technology, including a very accurate and fine line width, and a greater time for development. Accordingly, stacking technology has been proposed as another method to provide high-capacity semiconductor products.
The term “stack” in the semiconductor industry refers to stacking at least two semiconductor chips or semiconductor device packages. According to the stacking technology, a 128 MB dynamic random access memory (DRAM) may include two stacked 64 MB DRAM, or a 256 DRAM may include two stacked 128 MB DRAM. Additionally, the stacked semiconductor device packages have advantages including increased memory capacity, mounting density, and efficiency of mounting density and mounting area usage. Accordingly, research and development related to the stacked semiconductor device package has been increasing.
FIGS. 1 and 2 are cross-sectional views of a conventional semiconductor device package.
Referring to FIG. 1, a semiconductor device package includes stacked semiconductor chips 10a, 10b, and 10c, a printed circuit board (PCB) 20, bonding wires 35a, 35b, and 35c, a molding material 50, and solder balls 60.
The stacked semiconductor chips 10a, 10b, and 10c may respectively include bonding pads 12a, 12b, and 12c at active regions of their upper surfaces. Adhesive materials 40a and 40b are provided between the stacked semiconductor chips 10a, 10b, and 10c for adhesion therebetween. The stacked semiconductor chips 10a, 10b, and 10c may be mounted on the PCB 20 with an upper insulation layer pattern 24u using a mounting adhesive material 15.
The PCB 20 has a main body of a core material 22, and includes the upper insulation layer pattern 24u with bonding electrodes 26 and a lower insulation layer pattern 24l. The PCB 20 may include the bonding electrodes 26 corresponding to the bonding pads 12a, 12b, and 12c at an upper part.
The bonding wires 35a, 35b, and 35c may electrically connect the bonding pads 12a, 12b, and 12c with the corresponding bonding electrodes 26. The molding material 50 seals the PCB 20, the stacked semiconductor chips 10a, 10b, and 10c, and the bonding wires 35a, 35b, and 35c. The solder balls 60 disposed at a lower part of the PCB 20 are connected to an inner wire (not shown) of the PCB 20 such that connection for an external circuit such as a system board can be provided. Reference number 37 represents a connection ball that is formed during a wire bonding process in order to electrically connect the bonding pads 12a, 12b, and 12c with the corresponding bonding electrodes 26.
The above semiconductor device package has a structure in which the semiconductor chips 10a, 10b, and 10c having substantially the same size are stacked therein. There may be a spacer or an interposer in addition to the adhesive materials 40a and 40b between the stacked semiconductor chips 10a, 10b, and 10c. Furthermore, due to the bonding wires 35a, 35b, and 35c that electrically connect the bonding pads 12a, 12b, and 12c with the bonding electrodes 26, a minimum interval is required between the stacked semiconductor chips 10a, 10b, and 10c in order to accommodate the wires. Accordingly, this places a limitation on the ability to reduce the thickness of the semiconductor device package.
Referring to FIG. 2, a semiconductor device package includes stacked semiconductor chips 10d, 10e, and 10f, a PCB 20, bonding wires 35a, 35b, and 35c, a molding material 50, and solder balls 60.
The semiconductor chips 10d, 10e, and 10f may respectively include bonding pads 12d, 12e, and 12f at active regions of their upper surfaces. Adhesive materials 40c and 40d are provided between the stacked semiconductor chips 10d, 10e, and 10f for adhesion therebetween. The stacked semiconductor chips 10d, 10e, and 10f may be mounted on the PCB 20 with an upper insulation layer pattern 24u using a mounting adhesive material 15.
The PCB 20 has a main body of a core material 22 and includes the upper insulation layer pattern 24u with bonding electrodes 26 and a lower insulation layer pattern 24l. The PCB 20 may include the bonding electrodes 26 corresponding to the bonding pads 12d, 12e, and 12f at an upper part. The bonding pads 12d, 12e, and 12f and the bonding electrodes 26 may be electrically and sequentially connected or the bonding pads 12d, 12e, and 12f may be electrically connected to the bonding electrodes 26.
The bonding wires 35a, 35b, and 35c may electrically connect the bonding pads 12d, 12e, and 12f with the corresponding bonding electrodes 26. The molding material 50 seals the PCB 20, the stacked semiconductor chips 10d, 10e, and 10f, and the bonding wires 35a, 35b, and 35c. The solder balls 60 disposed at a lower part of the PCB 20 are connected to an inner wire (not shown) of the PCB 20 such that connection for an external circuit such as a system board can be provided. Reference number 37 represents a connection ball that is formed during a wire bonding process in order to electrically connect the bonding pads 12d, 12e, and 12f with the corresponding bonding electrodes 26.
The above semiconductor device package has a structure in which the semiconductor chips 10d, 10e, and 10f, having the respectively different sizes, are stacked therein. The sizes of the stacked semiconductor chips 10d, 10e, and 10f decrease from a lower part toward an upper part of the package. Unlike FIG. 1, there are only adhesive materials 40c and 40d between the stacked semiconductor chips 10d, 10e, and 10f. Accordingly, intervals between the stacked semiconductor chips 10d, 10e, and 10f are small compared to FIG. 1. However, the stacked semiconductor chips 10d, 10e, and 10f have sizes that decrease from the lower part toward the upper part such that mounting density of the semiconductor device package and the efficiency of mounting area usage are decreased.
The above described semiconductor device packages have a structure in which the bonding pads of the semiconductor chips are electrically connected to the bonding electrodes of the PCB through the bonding wires. Therefore, there is a limitation in stacking the semiconductor chips due to loop heights of the bonding wires. Furthermore, since intervals between the semiconductor chips are necessary, the thickness of the semiconductor device package increases as the number of stacked semiconductor chips is increased. Additionally, defects such as shorts between the bonding wires, opens of the bonding wires, shorts between the bonding wires and the adjacent bonding pads, and cracks of the semiconductor chips may occur during a wire bonding process. Furthermore, sweeping of the bonding wires may occur during a molding process. The present invention addresses these and other disadvantages of the conventional art.